1. Field of the Invention
The present invention generally relates to a buffered memory module and a method for testing same. More particularly, the present invention relates to a buffered memory module in which individual memory devices can be readily tested using a probe type testing method.
A claim of priority is made to Korean Patent Application No. 2003-41261 filed on Jun. 24, 2003, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference.
2. Description of Related Art
Memory modules are commonly used to operably configure multiple memory devices. Memory modules are often buffered to protect components within the module and/or to condition signals received by the module. Buffer circuits incorporated within semiconductor devices, such as memory modules, come in many forms, but generally receive an input signal and thereafter output the communicate the buffer input signal to an internal circuit. Thus, in a buffered memory module, the input signal, or some portion of the input signal, is transmitted through the buffer circuit. The data lines and components forming a semiconductor memory device can be effectively isolated using a buffer circuit. That is, signals applied to the data lines can be buffered. By buffering signals applied to the data line the problem of signal attenuation can be reduced, since buffering tends to alleviate problems associated with bus channel loading.
In spite of these advantages, buffered memory modules suffer from several shortcomings. First, the buffered memory module is relatively costly, since it incorporates separate buffer circuitry. Second, I/O signals communicated through a buffer circuit are delayed by some period of time. Third, it is difficult to test the individual memory devices once they are configured as part of a memory module.
The first shortcoming is not a significant problem in high-end applications where performance considerations outweigh cost considerations. The second shortcoming can be addressed by increasing the transmission speed of I/O signals between an external memory controller and the buffer circuit, or by temporally optimizing the signal transmission protocol used to communicate I/O signals to the buffer. However, the third shortcoming noted above is not so easily overcome.
FIG. 1 is a schematic view illustrating a conventional memory module lacking a buffer. The memory module 10 of FIG. 1 includes a memory controller 12, a plurality of semiconductor memory devices 14, and a board 16. The plurality of semiconductor memory devices 14 as arranged on board 16 to form the memory module are respectively connected to corresponding edge taps TAP1 through TAPn. Data is input and/or output between the plurality of semiconductor memory devices 14 and a memory bus (not shown) via the corresponding edge taps. Therefore, as shown in FIG. 1, for memory module 10, which lacks a buffer, it is relatively easy to access individual semiconductor memory devices. This ease of access greatly facilitates the testing of the individual memory devices. That is, since the data pins of the respective memory devices are directly connected to corresponding edge taps in a one-for-one manner, the individual memory devices arranged on memory module 10 can be readily tested by connecting test instrumentation, such as signal probes, to the edge taps. FIG. 2 is a schematic view illustrating a conventional memory module including a buffer. The memory module 20 of FIG. 2 includes a buffer circuit 22 connecting a plurality of memory devices 24 that are arranged on a board 26. Board 26 includes edge taps TAP1 through TAPn. In the buffered memory module 20 of FIG. 2, individual memory devices 24 are not connected directly to the edge taps TAP1 through TAPn, but are isolated by buffer circuit 22. That is, signal transmissions between the memory devices 24 and edge taps TAP1 through TAPn are made, without exception, through buffer circuit 22. Therefore, unlike memory module 10 of FIG. 1, the individual memory devices on buffered memory module 20 of FIG. 2 are not susceptible to testing using relatively simple test methods that require the connection of instrumentation, such as signal probes, to edge taps TAP1 through TAPn.